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Download

Windows

Version

Release Date

MSI installer

Size

Quality

Comment

2.7.41

2021-12-27

kretsim_installer-2_7_41.exe

20.5 MB

Gamma

Works with Windows 7 or later

2.7.8

2021-11-25

kretsim_installer-2_7_8.exe

20.5 MB

Beta

Works with Windows 7 or later

Linux

Version

Release Date

Linux 64-bit DEB pkg

Size

Quality

Comment

2.7.41

2021-12-27

kretsim-2.7.41-amd64.deb

14.5 MB

Gamma

Works with Ubuntu 20.04 or later, KDE or Gnome

2.7.8

2021-11-25

kretsim-2.7.8-amd64.deb

14.5 MB

Beta

Works with Ubuntu 20.04 or later, KDE or Gnome

2.6.52

2021-11-03

kretsim-2.6.52-amd64.deb

14.4 MB

Gamma

Works with Ubuntu 20.04 or later, KDE or Gnome

2.5.14

2021-10-17

kretsim-2.5.14-amd64.deb

14.3 MB

Beta

Works with Ubuntu 20.04 or later, KDE or Gnome*.

2.0.4

2021-09-09

kretsim-2.0.4-amd64.deb

13.2 MB

Beta

Works with Ubuntu 20.04 or later, KDE or Gnome*.

1.38.7

2021-09-01

kretsim-1.38.7-amd64.deb

12.6 MB

Beta

Works with Ubuntu 20.04 or later, KDE or Gnome*.

1.38.3

2021-08-30

kretsim-1.38.3-amd64.deb

12.6 MB

Beta

Works with Ubuntu 20.04 or later, KDE or Gnome*.

1.38.1

2021-08-30

kretsim-1.38.1-amd64.deb

12.6 MB

Beta

Works with Ubuntu 20.04 or later, KDE or Gnome*.

* A few menu item icons may not be displayed properly under Gnome.

Change Log

2.7.41

  1. New Features / Functions
    1. None
  2. Enhancements
    1. ALW.4 The <example> columns are less annoying
      ALW.3 The Simulation Control GUI is now more logical
      ALU.6 There are now menu options for entering and leaving sub-circuits.
      ALU.5 There are now zoom menus
      ALK.17 Text is now vertically centered in test editor TV-widget.
      ALK.16 Font i test editor test-vector widget now has a monospaced font.
  3. Fixed bugs
    1. ALW.2 Oscillator doesn’t generate the proper max simulation time figure when used unconnected.
      ALW.1 When an ordinary run is performed, the TSE shows green outputs to indicate OK results despite no verification is done.
      ALV.2 Stop Time in Sim Ctrl is not working properly.
      ALV.1 Column management in TSE is buggy; bad alignment and erroneous <example> removal.
      ALU.7 There is no export circuit menu option.
      ALU.4 Click-and-move comments do not unselect other GUI elements.
      ALU.3 Changes from sub-circuits ALWAYS progagate after navigation. Destroys signal info.
      ALU.2 Click on selected port doesn’t de-select it.
      ALU.1 Make sub-circuit may place new circuit out of view.
      ALT.5 When ports are added in a sub-circuit, and one moves up they’re all placed on top of each other.
      ALT.4 Comments can’t be cut!
      ALT.1 Port-to-port snapping is not working.
      ALO.1 Not all temp files are removed when quitting.
      ALK.15 Can’t scroll to right of last simulated value.
      ALK.14 Navigation up/down circuit hierarchy makes simulator forget some sub-circuits during simulation
      ALK.13 Space in TV spec becomes space in TV file.
      ALK.11 Selected ports on nodes are not unselected when another port on the same is clicked-to-move.
      ALK.10 Parameter editor needs ’tabbing’ sometimes for parameter value or key to ’take’.
      ALK.9 'Break segment’ is a bad name; wrong association. Should be ’Cut to stubs’ or something.
      ALK.8 Click-select-move ports on instances of same sub-circuit class is buggy.
      ALK.7 Windows temporary files are visible.
      ALK.6 When nets are copied and pasted, not all ports are connected correctly.
      ALK.5 When a sub-circuit isn’t a file circuit, one cannot move the ports all the way up.
      ALK.4 If shift is held down when another lasso is started, the original selection is unselected.
  4. Fixed Crashes
    1. ALT.3 'Undo’ before ’saved circuit’ crashes.
      ALR.2 It is possible to delete ports (using RMB-menu) on pre-defined components. Causes crash.
      ALR.1 It is possible to rename ports on pre-defined components. Causes crash.

2.7.8

  1. New Features / Functions
    1. Port for Windows.
  2. Fixed bugs
    1. AKW.1 Comments associated with gui elements are not deleted properly when element is deleted.
      AKG.1 Arrow keys in signal analyzer moves the whole signal box left/right.
      AKG.1 If oscillator is set of 71423 Hz, the clock switches phase by 180 degrees after two half-cycles.
      AKF.1 Circuit reset sequence buggy; port value reset may interfere with sub-circuit resets.
      AKC/7 The add button in the signal analyzer only allows selection of inputs...
      AKC.6 74LS867 and -191 have faulty internal reset procedure.
      AKC.5 Copied nodes duplicate port ID:s of old node.
      AKC/4 74LS867, LS191 and Oscillator does not reset properly at simulation start.

2.6.52

  1. New Features / Functions
    1. A time-aware memory inspection module.

  2. Enhancements
    1. All the tool windows are now proper, detachable or floating tool windows, who's position is saved between sessions.
    2. When a verification failure issue is selected in the issue window, the signal analyzer automatically zoomes in to that region.
    3. The 1, 2 and T cursors can now be set directly in the signal analyzer by using a RMB-enabled context menu.
    4. The T cursor has an entry for seeing/setting the T cursor value.
    5. Signal analyzer now indicates rapidly changing signals (this avoiding the alias phenomenon).
    6. A select-all menu option is added.
    7. One can now specify prefix 0x or $ to enter hex values, where this is not the default (e.g. in the parameter window).
    8. The test sequence editor now uses SI prefixes to show the time (ns, us, ms etc).
    9. The Net context menu has a delete option.
    10. Tool windows now toggles on short-cut invocation.
    11. Improved row management in test sequence editor, now less confusing.
    12. Signal analyzer now adheres to the standard shift/ctrl-enabled multi selection of rows.
    13. The displayed value Inout ports have been made more trouble-shooting friendly; it now shows what the net "on the other side" drives through the Inout.
    14. Alignment of the time column the generated TV files is improved to increase human readability.

  3. Fixed bugs
    1. AKC/2 Adjust time in TSE is not working.
      AKB/4 Copying nets terminating in ports on renamed nodes is broken.
      AKB/3 Can’t copy nets broken with NetStubs.
      AKB/2 Some icons missing in Gnome.
      AKB/1 Signal Analyzer window is not tall enough to show signals and scales.
      AKA/7 SA signals are sometimes drawn before the start of the row.
      AKA/6 Some SA rows for Inouts show only one value across range despite varying value.
      AKA/3 Cannot see the timing with high enough precision in signal analyzer and TSE and MainWindow
      AKA/2 Comparison between expected and real values in circuit verification is case sensitive
      AKA/1 Cannot enter comma (,) as a decimal separator i time entries
      AJ4/2 Not all test vectors show up as green when verified.
      AJ4/1 Test vector initialization sensitive to spaces when simulation starts.
      AJ2/15 Load contens-unit test for memory devices fails.
      AJ2/14 Inserting new lines in TSE generates empty vector values when saved, if previous/next values differ.
      AJ2/12 Pasting a copied circuit on another hierachial level misses some net segments.
      AJ2/11 Sometimes when a circuit is saved, there appears constructs like ”Circuit ’..’” or ”Circuit ’../..’”.
      AJ2/10 Save and reload TV file without outputs causes an error
      AJ2/8 Comparison between ’expected’ and ’real’ doesn’t take into account hexpansion (U vs UUUU).
      AJ2/7 Pin name input does not allow for ”/” character
      AJ2/6 Extract Test Sequence does not export pin names with component instance name prefixes.
      AJ2/5 New circuit doesn’t close memory viewers.
      AJ1/4 Kretsim tries unnecessarliy to find layouts where there are none, and produce annoying printouts.
      AJ1/3 ”No matching signal output” printouts
      AJ1/2 Memory components fail to load files sometimes.
      AJ1/1 When entering ’0’ for an 8-bit bus in the test editor, it is not expanded to ’00’ causing width alignment problems.
      AJT/5 Demux 1-to-4 has its bits reversed.
      AJT/4 Comments on components in sub-circuits disappear when going saving
      AJT/2 Vertical segment far to the right when attaching two ports (after a while?)
      AJT/1 Port and connector alignment is difficult.
      AJQ/5 On some KDE installations the header columns in the test sequence editor are not aligned.
      AJQ/1 Multi-select with shift sometimes leaves components ports selected when pressing on canvas.
      AIW/4 Signal Analyzer window toolwindow operation is inverted sometimes: not visible when mainwindow is
      active, and visible when some of the other tool windows are active.
  4. Fixed crashes
    1. AKC/3 KretSim crashes if a partially selected net with only one NetStub is copied and pasted.
      AJ3/2 Loading a ctc with certain syntax errors in it, crashes KretSim.
      AJ2/13 Multiple loads of a mal-formed TV file crashes KretSim.
      AJ2/3 Kretsim sometimes crashes when loading new circuit with a particular port / net design.
      AJ2/1 Can’t find port error when starting simulations hangs simulator if signals are present in signal analyzer.

2.5.14

  1. New Features
    1. New component: dual-port memory IDT7132LA.
    2. New component: an N-bit generic driver.
    3. Horizontal flip of Icon components
    4. A bin/hex check-box in the test editor.
    5. Right-menu option for locking/unlocking file-subcircuits in node context menu.

  2. Enhancements
    1. Test sequence editor now has a "save changes?" check
    2. Single 'Z' or 'X' in test vectors are now valid for multi-bit values, meaning "all bits are 'z''' (or 'x')
    3. Ctrl+mouse-wheel zooms in signal analyzer
    4. Mouse-wheel scrolls in signal analyzer
    5. Headers better organized in test sequence editor
    6. The delta-time column in the test sequence editor is now visually emphasized.
    7. Tool tips now show short-cuts in the signal editor.
    8. Consistent short-cuts ("Alt" used for all window operations)
    9. Multi-select in test editor is now more intuitive; requires shift for multi-select.
    10. Hexadecimal numbers consistently using A-F rather than a-f.
    11. Test vector specifications syntax is extended.
    12. Renamed ports now automatically renamed in test sequence editor.

  3. Fixed bugs
    1. AJA/1 Copy & paste on a different hierarchial layer gives a ”segment_layout” error
      AIY/1 11-bit values are not compared correctly in the verifier
      AIW/8 74LS191 doesn’t react properly to when up/down is undefined.
      AIW/5 File dialog for saving test vector says ’open’ on the button.
      AIP/1 Can’t save-as files.
      AIT/1 Value parse error ”LLLL XXXX” becomes ”LLL XXXX”.
      AIS/5 If is possible to rename a port on a locked sub-circuit by using F2.
      AIS/3 Multiple selected ports are not all added to test editor when chosen by RMB-menu.
      AIS/2 Values in test editor doesn’t show without the right circuit loaded.
      AIR/2 Entering a small ’x’ in the test edtior generates a faulty multi-bit value.
      AIR/1 Test sequence reported modified when it is not (after run).
      AIS/6 Lasso doesn’t select ports owned by components.
      AIK/51 Changes to sub-circuits are not propagated to other instances when they are file-subcircuits.
      AIO/51 When external circuits are added during the ”<Unknown>.ctc”-phase, and later saved, the import
      paths to these are not updated to be relative to the new file position.
      AHO/22 Cannot change between bus and pin IO models by changing the ’bus_io’ property on Demux1to4.
      AIO/52 When a file-subcircuit is locked and unlocked, the other instances should, but are not.
      AIL/6 When one adds inputs in the test editor one gets to add output too.
      AIL/5 ROI for ports too large in the vertical direction.
      AIL/4 Double-clicking component icons doesn't initiate a rename reliably.
      AIL/16 Test editor allows entering values that are too short.
      AIL/15 Test editor have ugly display of values when mixing bit-based and hex-based input group-of-four
      doesn't work.
      AIL/13 Test editor doesn't allow editing of columns which have no signal in the circuit.
      AIL/12 Space in test vector values cause problems in input. Should be allowed and removed.
      AIL/11 When using file dialogs the same place should be opened as the last one used both for test
      vectors and circuit files.
      AIL/10 The simulation / verification stop time is inconsistent with last test vector and last evaluation time.
      AIO/49 Comment on component moves behind component when component is moved.
  4. Fixed crashes
    1. AJQ/1 Kretsim crashes if one aborts a NetStub rename.
      AI4/1 Copy and paste "High" brings up parameter editor. If cancel, KretSim crashes.
      AIY/2 When a port is renamed from the parent circuit (which is attached to an internal net), the port is disconnected when one enters the circuit and if the component that is was attached to, is deleted, the program crashes.
      AIT/4 ¨I'm sorry, it seems like there has been a crash. An exception has been thrown: 'Error in
      /home-disk/thorman/projekt/TerminalCardForPet/.temp.107.TerminalCard.ctc:21:
      Net needs a name and at least one port.'
      AIS/8 Initial numbers in port assignment names in a test sequence file make KretSim crash.
      AIL/17 Crash after inserting mismatching value widths in test editor and then run it.

2.0.4

  1. Reworked the core event system, all simulations are now significantly faster.
  2. Fixed issue with ctrl/shift-clicking outside design element causes all elements to be de-selected.
  3. Fixed issue with parts of old test sequences remain after new circuit is opened.
  4. Added Cancel-button as an alternative when moving up from a circuit from an external, unssaved circuit.
  5. Fixed an issue with not being able to open datasheets in a locked circuit.

1.38.7

  1. Fixed crash upon test sequence load, when static port assignment names comprise a relative signal path.
  2. Fixed issue with ugly comments when files with comments, but without any layout information, are opened.
  3. Fixed issue with that test vector value comparisons do not expand hex characters after GUI edit prior to test.
  4. Fixed crash when opening a circuit in GUI lacking an associated layout file.

1.38.3

  1. Fixed issue with tool window behaviour.
  2. Fixed issue with not updated signal analyzer at time of new circuit creation.

1.38.1

  1. First public release