KretSim is a simulator for digital circuits. It has been in development since 2016, but has changed shape several times since then. The first public release was in September 2021.
The primary target audience is hobbyists (in particular people within the retro-computing community), non- or semi-professionals and education. The component directory contains many parts that were common on the 70s, 80s and 90s, like TTL logic and 8-bit CPUs and memories. The selection of the physical parts are bread-board friendly (e.g. DIP packages).
There is also a Youtube channel with some information about KretSim: https://www.youtube.com/channel/UClwSyaPo_9NFgxgMUCDrgdA
The main ideas behind KretsSim are:
- Physical timing model. All KretSim components come with a datasheet-based timing model. The components have a non-zero propagation delay (or delays), which makes it possible to attach an inverter input to its output. This will result in an oscillating circuit, with a frequency determined by the interter propagation delay.
- Hierarchical. A circuit may contain a sub-circuit, which may in turn contain other sub-circuits, and so forth. They are organized in hierarchically, like a file system, with similar operations for navigation; "entering" and "leaving" these circuits by the use of double-click or shortcuts. These sub-circuits may or may not be stored as separate files, which enables a structured development or larger designs.
- Typed. Each component (including circuits) have a type, e.g. "4-bit-adder'. If one instance of a component is modified, all instances of that type are automatically modified. So, if a 16-bit adder is to be made, four sub-circuits of '4-bit-adder' may be used. If one of those '4-bit-adder' circuits are changed, the others are updated automatically. This behaviour is similar to classes in programming languages.
- Command Line Support. KretSim comes with a command line version, capable of doing the same simulations and verifications as the GUI version. This enables automated testing of parts of the design. This philosophy extends to the file format of the ciruits (the CTC files), they are very much human readable. It is possible to use a text editor to edit the circuit files, or test sequence files.
- Functional components. The CPUs and memories in the component library actually work. It is possible to boot and run a program with them (albeit slowly).
- Ease of use. Since the author is lazy and don't like productivity hampering designs, some effort has been put into making the tool intuitive, and relatively well integrated. For example, for each 74-series component, CPU and memory, the corresponding datasheet is included, and available one click away. Other things include 'quarter'- (not quite 'semi') automated net layouts, automatic port and net highlights, extensive tool tip information, and generally an "integrated documentation" approach.
- Problem-finding approach. The purpose of the tool is to identify design problems, not to be an accurate representation of the physical operation (if there is a conflict between the two). For instance, if two different outputs drive the same net High, the result will be Undefined in this simulator, despite that the physical circuit will happily go high. The reason is that in most cases, two outputs driving the same net simultaneously is a design mistake and the designer should be given the opportunity to assess whether it is intended or not.
Why the name?
Every possible, reasonable or funny combination of digital, logic, circuit and simulation, in short or full form, was already taken. "Krets" is swedish for circuit.
Simulator and component models
(c) 2017-2021 Thorbjörn Jemander
MOS 6502 functional model
(c) 2018 Andre Weissflog, LibPNG License
WDC 65C02 functional model
(c) 2018 Andre Weissflog, LibPNG License
(c) 2021 Mathias Bergvall, LibPNG License
(c) 2014 Valentin Dudouyt
(c) 2022 David Griffith. GPL v3 License, included as aseparate binary.
(c) 2019 Simon Frankau. MIT License, included as aseparate binary.
The program is built using Qt Core, Ui and Widgets libraries, version 5.12, dynamically linked and in accordance with LGPL v.3